The backplane assembly of a high speed data processing and transmission system is a primary source of potentially unacceptable electronic noise and electromagnetic interference (EMI). This may involve signals in the frequency range of 150-175 Mhz but is not necessarily confined to this frequency range. The presence of noise and/or EMI can render a high speed data system functionally inoperative by causing misinterpretation of data bits by the inclusive circuitry, resulting in high bit-error-rates or system lock-up. Another detrimental effect of system noise is to cause unwanted fluctuations in the circuit supply voltage. This is particularly undesirable when the device comprises Gunning Transceiver Logic (GTL) because a lower supply voltage, 1.2-1.5 volts vs 3.3 volts, is implemented to achieve higher processing speeds.
The backplane noise is directly proportional to the rate of change of current flowing in the backplane circuit paths with respect to time, and to the inductance of these circuit paths, or L*(di/dt). This change in current flow is inherent in digital circuits due to the amplitude change of pulse waveforms with time. Specific pulse waveform characteristics that must be focused on in order to minimize or eliminate this system noise are the pulse rise and fall times, which determine the pulse edge rate or slew rate. Further, it is desired to provide the capability to increase the rise and fall times, thereby reducing the edge rate, in order to reduce the magnitude of di/dt. It is also desired to allow faster edge rates when system noise is not a prevalent problem or can otherwise be tolerated, an example of which would be a data transmission system operating in a lower frequency range than is applicable here.
The inductance of the circuit paths is a fixed physical parameter that is derived from backplane interconnections, such as printed wiring board (PWB) connectors, and interconnect wiring within the semiconductor devices. Such inductance is minimized in the backplane and device layout design process, leaving edge rate control as the primary means of alleviating system noise.
There currently exist several techniques for reducing system noise through use of edge rate control. Representative examples are given below with appropriate references:
Edge rate feedback CMOS output buffer circuit, U.S. Pat. No: 5,121,000. This invention includes an output driver stage that is formed of a pull-up transistor, a pull-down transistor, and feedback means. The feedback means is responsive to the output signal for controlling the rate of rise of the voltage at the gate electrode of the pull-down transistor so as to slow down its turn-on time when the output terminal is making a high-to-low transition, thereby reducing the ground bounce. The feedback means is preferably formed of a capacitor having a first plate connected to the output terminal and a second plate connected to the gate electrode of the pull-down transistor.
Controlled slew rate buffer, U.S. Pat. No. 5,138,194. This invention comprises a driver receiving voltage along a voltage supply line and includes feedback apparatus which senses the voltage supply line and slows the speed of the buffer when the noise level passes a given threshold.
CMOS driver having reduced switching noise, U.S. Pat. No. 5,241,221. This invention is comprised of a driver circuit with high- and low-impedance drive means which operate in parallel to effect a desired output transition. Adaptive control means respond to a threshold value of the output signal and turn off the low-impedance drive means in the course of the output transition. The low initial output impedance of the driver circuit effects rapid charging of a line capacitance, while toward the end of the output transition the higher output impedance of the driver circuit more closely matches the input impedance of a load circuit. This higher impedance dampens ringing and thereby reduces induced supply line noise.
CMOS buffer with controlled slew rate, U.S. Pat. No. 5,619,147. In this invention a feedback path from the output is coupled to transistors comprising a differential pair; the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback means to control the high-to-low and low-to-high transition rate of the output.
Slew Rate Controlled CMOS TIA/EIA-485 Transceiver, DS36C280, and RS423 Programmable Slew Rate Line Driver, DS9636A, National Semiconductor Corp. devices, have provisions for connecting an external resistor by the user, the value of which determines the rise and fall times of the output waveform.